1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) having an array of dynamic memory cells including a plurality of cascade-connected NOS transistors and data storing capacitors which are each connected at one end to one end of a corresponding one of the MOS transistors.
2. Description of the Related Art
A DRAM cell which is now practically used is constructed by one transfer gate NOS (insulated-gate) transistor connected to a word line and a bit line and one data storing capacitor connected to the MOS transistor.
In order to increase the integration density of the DRAM cells and lower the cost of each bit, the inventor of this application proposed a cascade-gate type semiconductor memory cell as shown in FIG. 1 or 2, for example (U.S. patent application Ser. No. 687,687).
The DRAM cell shown in FIG. 1 includes cascade-connected MOS transistors Q1 to Q4 and data storing capacitors C1 to C4 which are each connected at one end to one end of a corresponding one of the MOS transistors Q1 to Q4. Data stored in the capacitors C1 to C4 can be sequentially read out starting from the capacitor C1 which lies near one end of the cascade connection (readout/write-in node N1) and data on the node N1 can be sequentially written into the capacitors C1 to C4 starting from the capacitor C4 which lies in the farthest position from the node N1 by ON/OFF controlling the transistors Q1 to Q4 in a predetermined order.
In the DRAM cell shown in FIG. 2, a MOS transistor Q5 is additionally connected between one end of the transistor Q4 of the DRAM cell of FIG. 1 and a second node N2. Data stored in the capacitors C1 to C4 can be sequentially read out starting from the capacitor C1 which lies near the node N1 and supplied to the node N1 and data on the node N2 can be sequentially written into the capacitors C1 to C4 starting from the capacitor C1 which lies near the node N1 by ON/OFF controlling the transistors Q1 to Q5 in a predetermined order.
In the cascade-gate type memory cell shown in FIG. 1 or 2, plural-bit data can be stored for each bit, and when an array of the above memory cells is constructed, only one contact between the memory cell and the bit line is necessary for a plurality of bits so that an extremely high integration density can be attained in comparison with the conventional DRAM using an array of one-transistor/one-capacitor type cells and the cost for one bit can be significantly lowered.
When the DRAM is constructed by using the above cascade-gate type memory cells, data stored in the cell is read out in a destructive manner and therefore it is always necessary to rewrite data. However, in the above cascade-gate type memory cell, since the order of reading out data from or writing data into the capacitors of one memory cell is previously determined, it is forbidden to rewrite data into the capacitor of a memory cell immediately after stored data is read out from the same capacitor. That is, after data is read out from a capacitor in a memory cell, data cannot be rewritten into the capacitor until data is read out from the remaining capacitors of the same memory cell.
Therefore, when the DRAM is constructed by use of an array of the above cascade-gate type memory cells, it is necessary to provide means capable of sequentially rewriting (or writing) data after a plurality of bits have been time-sequentially read out from the memory cell.
With the above condition taken into consideration, the inventor of this application proposed a semiconductor memory device which includes storing means for temporarily storing plural-bit data time-sequentially read out from the above cascade-gate type memory cells when a DRAM is constructed by use of an array of the above cascade-gate type memory cells and in which the plural-bit data can be sequentially rewritten (or written) after the above readout operation is completed (U.S. patent application Ser. No. 721,255).
A difference between the operation speed of a DRAM and that of a microprocessor unit (MPU) continuously becomes larger and the difference between the data transfer speeds of the DRAM and the MPU causes a bottleneck which gives a large influence on the performance of the whole system. In order to solve this problem, various improvements have been made and a typical one of them is to use a high-speed memory (cache memory) which is connected between the MPU and a main memory in order to compensate for a difference between the cycle time of the MPU and the access time of the main memory and enhance the efficiency of usage of the MPU.
Three types of cache memories are now known: the first one is constructed by a static random access memory (SRAM) which is independent from both of the MPU and DRAM, the second one is constructed by an SRAM called an on-chip cache memory mounted on the MPU or embedded memory (in practice, an MPU having a cache memory may be provided with an SRAM on another chip), and the third one is constructed by SRAM cells mounted on the DRAM chip.
Since the second and third constructions among the above three types of cache memories are compact in size, they may be widely used for high-class devices such as work stations and personal computers. In particular, as the technique of mounting the cache memory constructed by SRAM cells on the DRAM chip in the third construction, the technique of providing SRAM cells for respective columns of a DRAM having one-transistor/one-capacitor cells and using the SRAM cells as a cache memory is disclosed in the article of 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp 79-80 "A Circuit Design of Intelligent CDDRAM with Automatic Write back Capability". Further, in the above article, the technique of writing back the content of the cache memory provided at the present time into a DRAM cell at a corresponding address when an address to be read out is not present in the cache memory (at the time of missing) and then reading out data from a DRAM cell at an address to be accessed is also described. The above cache mounting type DRAM can be used together with an MPU having a cache memory mounted thereon, and in this case, the cache memory on the DRAM is used as a second cache memory.
In the above-described cache mounting type DRAM, an extremely high average access speed in comparison with a normal DRAM can be attained and a large effect for solving the bottleneck of the system speed can be achieved. However, when compared with the conventional DRAM having one-transistor/one-capacitor cells, in the above DRAM, the chip size will become larger since it is necessary to use SRAM cells and associated circuits. In this respect, in the above article, it is described that the chip size will be 120% of the conventional case.
However, an increase in the chip size raises the cost of one bit and tends to weaken the desire of users to use the above DRAM even if it has an excellent performance.
With the above condition taken into consideration, the inventor of this application proposed a large number of concrete examples of storing means which can be used for temporarily storing data time-sequentially read out from the cascade-gate type memory cells and that the storing means can be used as a cache memory in the U.S. patent application Ser. No. 721,255.